Board layout of QFN for more reliable soldering

Introduction to QFN Packages and Soldering Challenges

Quad Flat No-lead (QFN) packages have become increasingly popular for integrated circuits due to their small size, good thermal and electrical performance, and low cost. However, the leadless nature of QFN packages presents some challenges when it comes to soldering them reliably to printed circuit boards (PCBs).

The small pitch and hidden solder joints under the package make QFNs prone to issues like poor wetting, solder bridging, voids, and uneven solder fillets. Proper PCB layout techniques are critical to achieving reliable solder joints and preventing defects when working with QFN packages.

In this article, we will discuss key considerations and best practices for designing the PCB layout for QFN packages to enable robust and reliable soldering. Topics covered include:

• Pad design and solder mask clearance
• Via placement and thermal relief
• Stencil aperture design
• Solder paste selection
• Reflow profile optimization

By understanding and applying these QFN-specific layout guidelines, you can greatly improve manufacturing yield and long-term reliability when using these increasingly common IC packages.

QFN Package Characteristics and Dimensions

QFN packages come in a variety of sizes and pin counts to suit different applications. Some common QFN package dimensions are shown in the table below:

The key characteristics of QFN packages that impact PCB layout and soldering include:

• Leadless terminations: QFN pads are flat and do not have any protruding leads, making solder joints hidden under the package body.
• Thermal Pad: Most QFNs have an exposed thermal pad on the bottom to enhance heat dissipation and provide a ground connection. This large pad requires proper vias and solder coverage.
• Small pitch: The 0.5mm lead pitch of QFNs is smaller than many other SMT packages, demanding tighter tolerances in the PCB layout and assembly process.

These unique attributes of QFNs necessitate specific layout techniques to ensure sufficient solder joint strength and reliability.

PCB Land Pattern Design for QFN

Pad Size and Shape

The land pattern is the arrangement of copper pads on the PCB that mate with the QFN package leads during soldering. Proper sizing and shaping of the pads are crucial for achieving good solder wetting and joint formation.

Typically, the pad width should be about 0.2-0.3mm larger than the package lead width to allow for some placement tolerance while maintaining sufficient area for solder fillets. The pad length can be the same as the lead length or slightly longer by 0.1-0.2mm.

Rounded or teardrop-shaped pads are preferable over rectangular pads for QFNs. The rounded ends help prevent solder bridging by providing a larger gap between adjacent pads. They also reduce stress concentration points and improve solder joint reliability.

Solder Mask Clearance

Solder mask is a polymer coating applied over the copper traces on a PCB, with openings around the pads where soldering occurs. For QFNs, it’s important to have enough solder mask clearance around the pads to allow for proper solder wetting and filleting.

A minimum solder mask opening of 0.05mm beyond the copper pad on all sides is recommended. This ensures the solder mask doesn’t overlap onto the pad and interfere with solder joint formation. The solder mask opening should follow the shape of the pad, including any rounded corners.

Thermal Pad and Via Design

The thermal pad on the bottom of a QFN package serves to dissipate heat from the IC die and provide a low-impedance ground connection. Proper design of the PCB land pattern for the thermal pad is critical for both thermal and electrical performance.

The PCB thermal pad should be slightly larger than the package thermal pad, typically by 0.5-1.0mm on each side. This allows for some registration tolerance and ensures adequate solder coverage even if the package is slightly misaligned.

To enhance thermal transfer and improve solder joint reliability, thermal vias are used to connect the PCB thermal pad to internal ground planes. These vias help conduct heat away from the QFN and anchor the solder joint mechanically.

The number and size of thermal vias depend on the package size and power dissipation. A typical recommendation is to use a grid of 0.3-0.5mm diameter vias spaced 1.0-1.5mm apart. The vias should have a solder mask opening larger than the drill size to allow solder wicking.

For thermal vias under the QFN package, it’s important to use thermal relief spokes to connect the via pads to the main thermal pad. Thermal reliefs are thin traces that restrict heat transfer during soldering, preventing the vias from wicking away too much solder and creating voids.

Stencil Design Considerations

Solder paste stencils are used in the SMT Assembly process to apply a controlled amount of solder paste onto the PCB pads before component placement. The stencil aperture design has a significant impact on the solder paste deposit volume and shape, which in turn affects solder joint formation.

Aperture Size and Shape

For QFN pads, the stencil aperture should be slightly smaller than the copper pad to allow for some solder wicking and filleting. A reduction of 0.1-0.2mm in length and width is typical.

The aperture shape should match the pad shape, including any rounded corners. This helps achieve a uniform solder paste deposit and avoid solder bridging between pads.

Thermal Pad Aperture Design

The large thermal pad on QFN packages requires a different aperture design than the perimeter pads. To prevent Solder Voids and ensure adequate solder coverage, the thermal pad aperture is typically divided into a grid pattern.

The grid spacing and aperture size depend on the thermal pad dimensions and solder paste properties. A common recommendation is to use a 1.0-1.5mm grid spacing with 50-70% aperture coverage. The apertures should avoid overlapping with the thermal vias to prevent solder wicking.

Some stencil designs also incorporate small “windowpane” openings in the thermal pad aperture to further improve solder paste release and reduce voiding.

Stencil Thickness and Material

The stencil thickness determines the volume of solder paste deposited onto the pads. For QFNs with a 0.5mm pitch, a stencil thickness of 0.125-0.150mm is typically used. Thinner stencils may be necessary for smaller packages or finer pitch.

Stainless steel is the most common material for solder paste stencils, offering good durability and paste release. However, for very fine-pitch QFNs or high-volume production, electroformed nickel or laser-cut polyimide stencils may be preferable for their superior edge definition and paste release.

Solder Paste Selection and Reflow Profile Optimization

Solder Paste Alloy and Particle Size

The choice of solder paste alloy and powder particle size can have a significant effect on the soldering performance and reliability of QFNs.

Lead-Free Solder alloys such as SAC305 (96.5% tin, 3% silver, 0.5% copper) are widely used for QFN soldering due to their good wetting properties and compatibility with lead-free component finishes. However, other alloys like SAC405 or low-silver SAC0307 may be preferred for specific applications or cost considerations.

For QFNs with a 0.5mm pitch, a Type 3 or Type 4 solder powder is recommended. These finer particle sizes (25-45 microns for Type 3, 20-38 microns for Type 4) enable better solder paste printing and reduce the risk of solder balling or bridging.

Reflow Profile Settings

The reflow soldering profile plays a critical role in achieving good solder joint formation and minimizing defects like voiding or head-in-pillow. The key parameters to control are:

• Preheat ramp rate: 1-2°C/second to avoid thermal shock and moisture-induced package cracking.
• Soak or thermal equalization time: 60-120 seconds at 150-180°C to allow the PCB and components to reach a uniform temperature before reflow.
• Reflow peak temperature and time above liquidus (TAL): 235-245°C peak for SAC305, with 30-90 seconds TAL to ensure complete solder melting and wetting.
• Cooling ramp rate: 2-4°C/second to promote grain refinement and prevent thermal stress build-up.

The exact profile settings will depend on the specific solder paste, PCB design, and oven capabilities. It’s important to conduct profile characterization and optimization runs to find the best settings for a given assembly.

QFN Layout and Soldering FAQ

Q1: What is the recommended pad size for a QFN package lead?

A1: The pad width should be 0.2-0.3mm larger than the lead width, while the pad length can be the same or 0.1-0.2mm longer than the lead length. This allows for placement tolerance while ensuring good solder fillets.

Q2: Why are thermal vias used under the QFN thermal pad?

A2: Thermal vias help conduct heat away from the QFN package and into the PCB ground planes, improving thermal dissipation. They also anchor the solder joint mechanically for better reliability.

Q3: What is the purpose of solder mask clearance around QFN pads?

A3: Solder mask clearance of at least 0.05mm around the copper pads is necessary to prevent the solder mask from overlapping onto the pads and interfering with solder wetting and joint formation.

Q4: How should the solder paste stencil aperture be designed for the QFN thermal pad?

A4: The thermal pad aperture should be divided into a grid pattern, typically with 1.0-1.5mm spacing and 50-70% coverage. This helps achieve uniform solder paste deposition and reduces the risk of voiding.

Q5: What are the key parameters to control in the reflow soldering profile for QFNs?

A5: The critical reflow profile parameters for QFN soldering are the preheat ramp rate (1-2°C/s), soak time (60-120s at 150-180°C), peak temperature (235-245°C for SAC305), time above liquidus (30-90s), and cooling ramp rate (2-4°C/s). Proper control of these settings ensures good solder joint formation and minimizes defects.

Conclusion

Quad Flat No-lead (QFN) packages offer many benefits for miniaturization and performance, but their unique characteristics demand careful consideration in PCB layout and soldering process design. By following the guidelines and best practices outlined in this article, you can optimize your QFN board layout for more reliable soldering.

Key aspects to focus on include:

• Proper pad size, shape, and solder mask clearance for good solder wetting and filleting.
• Thermal pad and via design for efficient heat dissipation and mechanical anchoring.
• Solder paste stencil aperture design, especially for the thermal pad, to ensure uniform paste deposition and minimal voiding.
• Selection of appropriate solder paste alloy and particle size for the package pitch and assembly process.
• Optimization of the reflow soldering profile, particularly the preheat, soak, peak temperature, and cooling stages.

By understanding and applying these QFN-specific layout techniques, you can greatly improve manufacturing yield, solder joint reliability, and overall product quality when using these advanced IC packages.