What Causes Lifted Pads on PCBs?
There are several potential causes of lifted pads on printed circuit boards:
Incorrect Hole Drilling
One common cause is incorrect hole drilling during PCB fabrication. If the holes for through-hole components or vias are drilled off-center from the pads, there will be less bonding area between the pad and board. This makes the pad-to-board adhesion weaker and more prone to lifting.
Recommended drill hit location:
| Pad Size | Ideal Hit Location | Acceptable Tolerance |
|---|---|---|
| ≤ 20 mils | Center of pad | ± 5 mils |
| 20-40 mils | Center of pad | ± 7 mils |
| > 40 mils | Center of pad | ± 10 mils |
Poor Bonding During Lamination
Lifted pads can also occur due to poor bonding between the copper layers and insulating substrate during the lamination process of multi-layer boards. If the lamination temperature, pressure, or time is incorrect, or if there are contaminants present, the adhesion between the layers will be compromised.
Proper lamination parameters depend on the specific materials used, but typical values are:
| Parameter | Value Range |
|---|---|
| Temperature | 350-375°F |
| Pressure | 275-400 PSI |
| Time | 60-90 minutes |
Preheat and cool down ramps of 5-8°F per minute are also important to avoid thermal shock.
Overstressed Pads During Soldering
Excessive thermal or mechanical stress during component soldering can also lead to lifted pads. If the soldering temperature is too high or applied for too long, the pad can delaminate from the board. Applying too much force when inserting through-hole component leads or using an oversized soldering iron tip can also overstress and lift the pads.
Recommended soldering parameters for common components:
| Component | Soldering Temperature | Soldering Time |
|---|---|---|
| Chip resistors/capacitors | 235-245°C | 3-5 sec |
| SOICs, QFPs | 240-250°C | 5-10 sec |
| PLCCs | 250-260°C | 10-15 sec |
Trace Cracking and Tearing
Lifted pads sometimes occur together with cracked or torn traces, especially on thinner boards with finer pitch traces. Trace cracking can be caused by depaneling, vibration, impact, or bending the board. Cracks often propagate from the trace to the pad, weakening the pad adhesion.
Typical precautions to avoid trace cracking:
- Use a board thickness of ≥ 0.8mm for boards with trace width/spacing ≤ 4/4 mils
- Support boards > 6 inches long during depaneling and handling
- Avoid more than 3 lamination cycles for MLBs
- Keep fabs and assembly cool and dry to prevent thermal cycling
Contamination and Moisture
Finally, contamination of the board or pads with oils, salts, or other residues can degrade the adhesion of the pads over time. Moisture absorption into the board, components or coatings can also cause swelling and stress that leads to pad lifting.
Sources of contamination to control:
- Oils from handling, router bits, drill bits
- Salts from human skin
- Acid fumes, solder flux residues
- Adhesives, coatings, sealants
- Dust and debris
Baking PCBs at 125°C for 4-6 hours prior to applying any coatings helps remove absorbed moisture.
Identifying Lifted Pads
Lifted pads can be detected through visual inspection, although very small lifted pads may require magnification to see. A lifted pad will appear to be separated from the board surface, often protruding up at an angle. The severity can range from a slight delamination along one edge to the pad being completely detached from the board.
Other signs that can indicate a lifted pad include:
- Cracks or discoloration on the pad or adjacent trace
- A trace or lead that has lifted up with the pad
- Measling or blistering of the solder mask around the pad
- Solder that has wicked under the pad during reflow
Lifted pads can also be detected with electrical tests like continuity or isolation resistance measurements. An open circuit or latent high resistance can reveal lifted pads that are not visible.
X-ray inspection is another method to find lifted pads that are hidden under components or not detectable optically.
Repairing Lifted Pads
Minor lifted pads that are not completely detached can sometimes be repaired by pressing the pad back down and re-bonding it with adhesive or epoxy. Applying liquid epoxy under and around the pad, then curing it at 150°C for an hour can restore the mechanical bond in some cases.
For pads that have lifted with the component lead or trace still attached, careful soldering can be used to reattach the lifted pad and lead. First apply flux to the pad and solder a fine wire to bridge the lifted pad to an adjacent trace or component lead. Then gently press the pad down while heating the solder bridge with a fine tip iron until the solder reflows and makes a new connection.
If the pad is completely separated or has lifted multiple times, the only repair option is to jumper wire around the lifted pad. Scrape off the solder mask next to the pad to expose the trace and solder a fine gauge wire to bridge the trace to the component lead.
Jumper wire repair procedure:
- Scrape solder mask to expose 10-20 mils of the trace near the pad
- Clean any solder or debris off the trace and component lead
- Pre-tin the trace and lead with a small amount of solder
- Strip and pre-tin a 28-30 AWG wire to span the distance
- Solder one end of the wire to the exposed trace
- Solder the other end to the component lead
- Trim any excess wire
- Apply epoxy or UV mask over the jumper wire for support
For multi-layer boards with lifted via pads, there may not be an accessible trace to jumper to. In this case, the only option is to drill out the via and replace it with a through-hole pin and pad.
While lifted pads can often be repaired, the process is time consuming and the connection may not be as robust as the original. Preventing pad lifting through good design and process control is always preferable to repairing it after the fact.
Preventing Lifted Pads in PCB Design
Certain PCB design choices can help minimize the risk of lifted pads, including:
Using Oversized or Teardrop Pads
Enlarging the SMT pads to 10-20% larger than the minimum required for the component increases the bonding area and adhesion strength. Teardrop shaped pads that flare out where they meet the trace also prevent stress concentrations and peel-up forces at that point.
Recommended pad size increases:
| Pad Type | Minimum Size | Oversized |
|---|---|---|
| Chip (0201) | 8 x 12 mils | 10 x 15 mils |
| Chip (0402) | 16 x 20 mils | 20 x 25 mils |
| Chip (0603) | 20 x 24 mils | 25 x 30 mils |
| SOICs (50 mil pitch) | 18 x 50 mils | 22 x 60 mils |
| QFPs (25 mil pitch) | 12 x 50 mils | 15 x 60 mils |
Optimizing Hole Size and Placement
For through-hole pads, making the drilled hole diameter as close as possible to the lead diameter maximizes the area for solder filleting and pad adhesion. Centering the hole in the middle of the pad also provides the most balanced bonding.
Recommended drill to lead diameter ratio:
| Lead Diameter | Drill Diameter | Drill/Lead Ratio |
|---|---|---|
| 8-12 mils | Lead + 8 mils | 1.6-2.0 |
| 12-30 mils | Lead + 10 mils | 1.3-1.8 |
| 30-60 mils | Lead + 12 mils | 1.2-1.4 |
Thieving Copper Balance
On multi-layer boards, balancing the copper area on each layer and adding copper thieving where needed minimizes warping or uneven expansion/contraction between the layers. This helps prevent localized stresses that can cause pad lifting.
Ideally, copper coverage should be 50-70% and balanced within 10% on each layer. Copper pours, hatched polygons, or dot patterns can be added to unused areas to compensate for low copper layers.
Selecting Sufficient Board Thickness
Using a thicker board or additional layers provides more mechanical strength and stiffness to prevent flexing or trace cracking that can lead to lifted pads. A good rule of thumb is to use at least 0.8mm thickness for every 4 copper layers, with absolute minimum thicknesses of:
- 0.4mm for 1-2 layers
- 0.6mm for 4 layers
- 0.8mm for 6-8 layers
- 1.0mm for 10-12 layers
Avoiding Acute Trace Angles
Traces that meet pads at 90° angles create stress concentration points that are prone to cracking. Using curved, rounded trace entrances or 45° corners minimizes this stress.
Recommended minimum trace to pad radii:
| Trace Width | Radius |
|---|---|
| 2-4 mils | 5 mils |
| 4-8 mils | 10 mils |
| 8-12 mils | 15 mils |
Preventing Lifted Pads in PCB Fabrication
In addition to design considerations, controlling the PCB fabrication process is key to avoiding lifted pads.
Drill Hit Accuracy
Precise drilling requires the use of high quality, well-maintained drill bits and good drill hit registration. Drill bit run-out and wander needs to be routinely checked and bits changed out or re-pointed when they exceed tolerances.
The x-ray drill hit inspection should verify:
- Hole to pad concentricity within 5 mils
- Hole breakout is < 90° of the pad circumference
- No nailheading or tear-out of the holes
Lamination Control
The key variables for multi-layer lamination are the preheat and cool down ramp rates, the lamination temperature, pressure, and time. These need to be tightly controlled and optimized for the material and stack-up used.
Common FR-4 lamination recipe:
| Step | Setting |
|---|---|
| Vacuum | 28 in-Hg for 15 min |
| Clamping Pressure | 300 PSI |
| Heating Ramp | 8-10°F/min to 350°F |
| Dwell Temperature/Time | 350-360°F for 60 min |
| Cool Down Ramp | 5-8°F/min to 150°F |
Prepregs should be kept sealed until use and baked at 120-150°C for 1-2 hours before lamination to remove moisture.
Solder Mask Control
Applying the solder mask at the correct thickness and cure profile is important to avoid problems like measling or delamination that can contribute to pad lifting. The mask also needs good registration to the pads to maximize the bonding area.
Typical solder mask parameters:
| Mask Type | Thickness | Cure Temp | Cure Time |
|---|---|---|---|
| LPI | 0.5 mils | 150°C | 60 min |
| Dry film (vacuum) | 1.0 mils | 160°C | 30 min |
| Dry film (tenting) | 2.0 mils | 160°C | 30 min |
The mask also needs good adhesion to the copper, typically > 4 lbs peel strength.
Thermal Cycle Stress Testing
Subjecting sample PCBs to accelerated thermal cycling during qualification or batch testing can help screen for lifted pad issues. IPC-TM-650 specifies cycling bare boards between -40°C and 125°C for 100-400 cycles and then inspecting for any lifted pads or other delamination.
Typical thermal cycle test profile:
| Step | Setting |
|---|---|
| Low Temperature | -40°C |
| High Temperature | 125°C |
| Ramp Rate | 2-5°C/min |
| Dwell Time | 10-20 min |
| Number of Cycles | 100-400 |
Boards that pass this test should be robust against lifted pads from thermal stresses during assembly or operation.
FAQ
What is the most common cause of lifted pads?
The most common causes are incorrect drill hit location and overstress during soldering. Problems from drilling are typically systematic across a panel or lot, while pad lifting from soldering may be more random.
Can you always see lifted pads visually?
Not always – lifted pads under components or minor ones at the edge of a pad may not be visible without magnification or x-ray. Electrical testing can detect lifted pads by a high resistance or open circuit.
How much of a process window is there for reflow soldering to avoid pad lifting?
In general, exceeding the reflow soldering temperature by more than 10-20°C or the dwell time by 20-30% can cause lifted pads, especially for larger components. Following the paste manufacturer’s recommended profile for the specific components is advisable.
Will a thicker PCB always prevent lifted pads?
A thicker board will be more mechanically robust but it is still possible to get lifted pads from contamination, poor drilling, or extreme soldering conditions. Also, using an excessively thick board can cause its own issues like difficulty drilling small vias.
Is pad lifting more common in lead-free assembly?
The higher soldering temperatures needed for lead-free can increase the risk of pad lifting compared to leaded soldering. However, as long as the process is well controlled and optimized, the risk can be mitigated. Many companies are successfully building lead-free products without significant lifted pad issues.
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